Duties
- Microarchitecture and design in Verilog/System Verilog.
- Define and own ASIC design methodologies.
- Integrate complex IPs developed by internal groups as well other vendors.
- Block and Chip level RTL verification and gate-level netlist testing.
- Support other ASIC design activities such as Lint, CDC checks, formal
verification,synthesis, and DFT.
- Support back-end engineers with timing-closure and ECOs.
- Chip bring up, validation and debug.
- Support Firmware development and Applications teams.
Requirements
- BS/MS in Electrical/Computer Engineering.
- BS degree with 2+ years of relevant experience, or recent graduate with MS
degree.
- Knowledge of Verilog/System Verilog, UVM.
- Fluent with Verilog and System Verilog.
- Good oral and written communication skills.
- Knowledge/experience with Python is nice to have.
- Knowledge of ASIC EDA tools such as Synopsys DC, Cadence Incisive (IES),
Verdi etc.is nice to have.
