Develop verification environment and coverage closure;
Compile design documentation and integration guide;
Support co-simulation;
Support wafer level testing and silicon evaluation.
Job Requirements
Bachelor or above in Electronic Engineering or equivalent;
5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations;
Knowledge of SoC and embedded system;
Candidate with less experience will be considered as Digital Design Engineer.
All applications will be treated in strict confidence and for recruitment purpose only.
